Modern power circuits require power rectifiers with improved power switching performance. For high voltage applications, P+/N rectifiers with high switching speeds are often used when high breakdown voltages and high operating temperatures are desired. For low voltage applications, Schottky barrier rectifiers are often used when high switching speeds and very low forward voltage drops are desired. The Schottky barrier rectifier is a majority carrier device which allows little reverse current flow during recovery. Unfortunately, Schottky barrier rectifiers suffer from undesirably high reverse leakage current when operating at elevated temperatures.
Several modifications have been introduced to improve the blocking capability of Schottky rectifiers. One such improvement is the junction barrier Schottky (JBS) rectifier, which combines a P/N junction grid with Schottky barrier regions small enough that the expanding space charge region from the P+/N junction grid leads to elimination of the Schottky barrier lowering caused by the image charge. The JBS rectifier provides an approximately 50% net reduction in leakage current for the same chip area and forward voltage drop. This equates to an approximately 11 degrees Kelvin improvement in the power dissipation curve for a diode operating at a 50% duty cycle.
Another such improvement is trench Schottky, which is useful for higher voltage applications in which the forward voltage drop exceeds 0.7 volts and the JBS rectifier ceases to operate as a majority carrier device. For example, the trench MOS barrier-controlled Schottky (MBS) rectifier has a lower forward voltage drop than the P-i-N rectifier for breakdown voltages up to 250V and still operates as a majority carrier device.
In addition to these high voltage applications, there is an increasing demand for low voltage applications, for which conventional trench Schottky is not well suited. Trench Schottky requires that, in the blocking state, the inner trenches are sufficiently closely spaced, and the adjacent areas of the body portion are sufficiently lowly doped, that the depletion layer formed in the body portion depletes the intermediate areas of the body portion between the trenches at a smaller voltage than the breakdown voltage. In that way, the reverse voltage blocking characteristic is improved. Unfortunately, it also results in a significant reduction in the area available for the Schottky barrier because the trench may consume as much as 50% of the area available on the chip.
U.S. Pat. No. 6,979,861 discloses a MOS transistor-like two terminal device. The vertical structure and forward current flow pattern of this device are shown in FIG. 2 of the patent. The device is a two-terminal device; the upper electrode provides direct contact with an N+ source, a gate electrode, and a P-body, while the lower electrode is a drain electrode. Forward conduction is achieved when positive voltage is applied to the top electrode. Positive bias on the gate inverts the P-body under the gate into an N-channel which allows forward current to flow. Negative bias on the gate does not cause the N-channel to form. The P-base/N-drift region becomes reverse-biased pin diode and supports a reverse voltage. Unfortunately, this device suffers from its parasitic N+/P/N bipolar structure resulting in reduced dV/dt performance.